In various digital electronic equipments, e.g., personal computer, mobile telephone, video equipment and/or audio equipment, etc., there is provided multi-chip circuit module on which semiconductor chips such as various IC elements or LSI elements, etc. are mounted. In various digital electronic equipments, finning of circuit pattern, miniaturization of IC package, rapid improvement in integration scale, multi-pin structure and/or improvement in mounting method, etc. have been provided so that miniaturization and high level function of the multi-chip circuit module are realized. Thus, miniaturization and light weight, and/or thin structure are realized, and high performance, high level function, multi-function and/or high speed processing, etc. have been realized.
In multi-chip circuit modules, there are also circuit modules where the so-called system LSI on which circuits having different functions, e.g., logic function and memory function or analog function and digital function, etc. are mounted are constituted. In the multi-chip circuit modules, there are also circuit modules in which the so-called multi-chip circuit module where functional blocks of respective processes are manufactured as individual semiconductor chips and these semiconductor chips are mounted on the same board is constituted.
Meanwhile, in the multi-chip circuit module, in order to realize further improvement in performance, realization of high speed of microprocessor and/or realization of high density of signal wiring between memory chips are required, and it is necessary to take a measure for the problem of wiring delay. In the multi-chip circuit module, even if clock frequency above GHz is realized within respective elements (chips), clock frequency must be lowered in digit units owing to the problems such as signal delay and/or reflection, etc. based on wirings between chips. In addition, in the multi-chip circuit module, realization of high speed of signal wiring and/or realization of high density are provided to thereby also require countermeasure for, e.g., EMI (electromagnetic interference) or EMC (electromagnetic compatibility). Accordingly, in the multi-chip circuit module, it is necessary to provide realization of high integration and/or high performance on the whole as a system technology including mounting technology for package or board, etc. in addition to improvement in formation technology for chip.
Hitherto, as the multi-chip circuit module, there is a circuit module as shown in FIG. 1. The circuit module shown in FIG. 1 is a multi-chip circuit module 100 of the flip-chip type in which plural semiconductor chips 102A, 102B are mounted on a principal surface 101a of an interposer 101. The multi-chip circuit module 100 is adapted so that suitable circuit patterns, lands and/or input/output terminals, etc. are respectively formed on the surface principal surface 101a and the back principal surface 101b of the interposer 101 are formed. In the multi-chip circuit module 100, at the principal surface 101a of the interposer 101, respective semiconductor chips 102 are mounted in the state where they are respectively flip-chip connected on predetermined lands 103 and connecting portions are covered by underfill 104 on the principal surface 101a of the interposer 101. At the multi-chip circuit module 100, solder balls 105 are respectively mounted at lands formed at the principal surface 101b of the interposer 101, and reflow solder processing is implemented in the state where they are mounted on, e.g., mother board, etc. to melt and solidify the solder balls 105. Thus, the multi-chip circuit module is mounted.
As described above, at the conventional multi-chip circuit module 100, plural semiconductor chips 102 are mounted in lateral arrangement state on the principal surface 101a of the interposer 101. However, wirings which connect respective semiconductor chips 102 are restricted by circuit patterns formed at the interposer 101 side. In the multi-chip circuit module 100, with realization of multi-function and realization of high speed, etc. of the apparatus where this module 100 is mounted, a large number of semiconductor chips 102 are provided. Thus, a larger number of wirings are required. In the multi-chip circuit module 100, because pitch of wiring pattern formed at the interposer 101 manufactured by the general board (substrate) manufacturing technology is large value of the order of about 100 μm even at the minimum by restriction of manufacturing condition, etc., interposer 101 of large area or caused to be of multi-layer structure is required in the case where a large number of connections are made between plural semiconductor chips 102.
In the multi-chip circuit module 100, in the case where multi-layered interposer 101 is used, interlayer connection through via and/or connection between respective semiconductor chips 102 are conducted. In this case, since its hole diameter is about 50 μm even at the minimum from the processing condition, and land diameter is also about 50 μm even at the minimum, large-sized interposer 101 is required. For this reason, at the multi-chip circuit module 100, there were the problems that wiring pattern formed at the interposer 101 which connects respective semiconductor chips 102 is elongated, and many vias are formed so that L▪C▪R components become large.
For example, in the manufacturing process for the semiconductor device, there has been also proposed a technology in which an insulating layer is formed as film on a silicon substrate thereafter to form fine wiring pattern via dry etching step of forming via grooves and wiring grooves and film formation step for conductive metal layer. In such wiring formation method, first dry etching processing is implemented to an insulating layer to form a large number of via grooves, and second dry etching processing is implemented to form wiring grooves as pattern. In this wiring formation method, copper film layer is formed by, e.g., plating on the entire surface of the insulating layer thereafter to implement polishing processing to this copper film layer to thereby form via holes and a predetermined wiring pattern.
In accordance with such wiring formation method, as compared to the typical wiring formation method of forming via holes by machining or laser processing and implementing etching processing to copper foil to form circuit pattern, it is possible to form fine and high density wiring pattern as multi-layer structure. In this wiring formation method, it is necessary to implement precise first dry etching processing and precise second dry etching processing having depths of groove different from each other, and it is difficult to apply this method to manufacturing process for typical multi-layer wiring board. In addition, in accordance with this wiring formation method, since wiring layers are formed on silicon substrate as multi-layer structure, there are the problem that the mounting structure onto mother board, etc. becomes complicated so that realization of miniaturization becomes difficult, and wiring pattern is also elongated.